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Found 475 question(s)
Q96
NAT
GATE
CS
Medium
1 Mark
2024
COA â I/O Interface
A keyboard is used at 1 keystroke per second. In polling, it polls every 10 ms consuming 100 Ξs each poll, plus 200 Ξs to process a stroke (T1 is fraction of sec spent). In interrupt, it takes 1 ms to service/process per keystroke (T2 is fraction of sec spent). The ratio T1/T2 is
Q97
MSQ
GATE
CS
Medium
2 Marks
2024
COA â Cache Memory
Consider two set-associative cache memory architectures: WBC, which uses the write back policy, and WTC, which uses the write through policy. Both of them use the LRU (Least Recently Used) block replacement policy. The cache memory is connected to the main memory. Which of the following statements is/are TRUE?
Q98
NAT
GATE
CS
Medium
2 Marks
2024
COA â Amdahl's Law
The baseline execution time of a program on a 2 GHz single core machine is 100 ns. The code corresponding to 90% of the execution time can be fully parallelized. The overhead for using an additional core is 10 ns when running on a multicore system. The number of cores that minimize the execution time of the program is
Q99
NAT
GATE
CS
Medium
1 Mark
2024
COA â Pipelining
Consider a 3-stage pipelined processor having a delay of 10 ns, 20 ns, and 14 ns for the first, second, and third stages. Assume no other delay and no pipeline hazards. One instruction is fetched every cycle. The total execution time for executing 100 instructions on this processor is ___ ns.
Q100
NAT
GATE
CS
Hard
2 Marks
2024
DBMS â Indexing