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Q406
MCQ
GATE
CS
Hard
2 Marks
2020
CN → Network Routing
An organization requires a range of IP addresses to assign one to each of its 1500 computers. The organization has approached an Internet Service Provider (ISP) for this task. The ISP uses CIDR and serves the requests from the available IP address space 202.61.0.0/17. The ISP wants to assign an address space to the organization which will minimize the number of routing entries in the ISP's router using route aggregation. Which of the following address spaces are potential candidates from which the ISP can allot any one to the organization? I. 202.61.84.0/21 II. 202.61.104.0/21 III. 202.61.64.0/21 IV. 202.61.144.0/21
Q407
MCQ
GATE
CS
Medium
1 Mark
2020
CN → Network Routing
Consider the following statements about the functionality of an IP based router. I. A router does not modify the IP packets during forwarding. II. It is not necessary for a router to implement any routing protocol. III. A router should reassemble IP fragments if the MTU of the outgoing link is larger than the size of the incoming IP packet. Which of the above statements is/are TRUE?
Q408
NAT
GATE
CS
Hard
2 Marks
2020
CN → Transport Layer
Consider a TCP connection between a client and a server with the following specifications: the round trip time is 6 ms, the size of the receiver advertised window is 50 KB, slow-start threshold at the client is 32 KB, and the maximum segment size is 2 KB. The connection is established at time t=0. Assume that there are no timeouts and errors during transmission. Then the size of the congestion window (in KB) at time t+60 ms after all acknowledgements are processed is
Q409
MCQ
GATE
CS
Medium
1 Mark
2020
COA → I/O Interface
Consider the following statements. I. Daisy chaining is used to assign priorities in attending interrupts. II. When a device raises a vectored interrupt, the CPU does polling to identify the source of interrupt. III. In polling, the CPU periodically checks the status bits to know if any device needs its attention. IV. During DMA, both the CPU and DMA controller can be bus masters at the same time. Which of the above statements is/are TRUE?
Q410
MCQ
GATE
CS
Hard
2 Marks
2020
COA → Cache Memory