PYQBOOK

Filter Questions

Exam

Branch

Paper-Name

Subject

Topic

Found 475 question(s)

Q411 NAT GATE CS Hard 1 Mark 2020

COA → Cache Memory

A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is

Enter Numerical Answer:

Q412 MCQ GATE CS Hard 2 Marks 2020

COA → Cache Memory

A computer system with a word length of 32 bits has a 16 MB byte-addressable main memory and a 64 KB, 4-way set associative cache memory with a block size of 256 bytes. Consider the following four physical addresses represented in hexadecimal notation. A1 = 0x42C8A4, A2 = 0x546888, A3 = 0x6A289C, A4 = 0x5E4880. Which one of the following is TRUE?

Choose One:

A) A1 and A4 are mapped to different cache sets.

B) A2 and A3 are mapped to the same cache set.

C) A3 and A4 are mapped to the same cache set.

D) A1 and A3 are mapped to the same cache set.

Q413 NAT GATE CS Hard 1 Mark 2020

COA → Cache Memory

A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is

Enter Numerical Answer:

Q414 NAT GATE CS Hard 2 Marks 2020

COA → Pipelining

Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipelined processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instructions. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipelined processor (round off to 2 decimal places) is

Enter Numerical Answer:

Q415 MCQ GATE CS Medium 1 Mark 2020

COA → CPU Architecture

Consider the following data path diagram. Consider an instruction: R0 <- R1 + R2. The following steps are used to execute it over the given data path. Assume that PC is incremented appropriately. The subscripts r and w indicate read and write operations, respectively. 1. R2_r, TEMP1_r, ALU_add, TEMP2_w 2. R1_r, TEMP1_w 3. PC_r, MAR_w, MEM_r 4. TEMP2_r, R0_w 5. MDR_r, IR_w. Which one of the following is the correct order of execution of the above steps?

Choose One:

A) 2, 1, 4, 5, 3

B) 1, 2, 4, 3, 5

C) 3, 5, 2, 1, 4

D) 3, 5, 1, 2, 4

1
2
3
.....
81
82
83
84
85
.....
93
94
95